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| ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 1 of 45 1-888-824-4184 ? ia82527 serialcommunicationscontroller ? canprotocol datasheet documentversion1.0
ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 2 of 45 1-888-824-4184 ? copyright?2007byinnovasicsemiconductor,inc. publishedbyinnovasicsemiconductor,inc. 3737princetondrivene,suite130,albuquerque,nm 87107 innovasicsemiconductor,inc. office: 505.883.5263 3737princetondrivene,suite130 fax: 505.883.547 7 albuquerque,nm871074237 tollfree: 1888.824.418 4 www.innovasic.com aniso9001:2000company intel ? isaregisteredtrademarkofintelcorporation. miles?isatrademarkofinnovasicsemiconductor,i nc. motorola ? isaregisteredtrademarkofmotorola,inc. ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 3 of 45 1-888-824-4184 ? tableofcontents contents 1. introduction.................................... ................................................... .................................. 5 1.1 generaldescription ............................ ................................................... ..................... 5 1.2 features ....................................... ................................................... ........................... 6 2. packagingandpindescriptions .................. ................................................... .................... 7 2.1 packagesandpinouts ........................... ................................................... .................. 7 2.2 pin/signaldescriptions ........................ ................................................... .................. 10 3. maximumratings,thermalcharacteristics,anddc parameters..................................... 18 4. functionaldescription .......................... ................................................... ......................... 21 4.1 hardwarearchitecture .......................... ................................................... ................. 21 4.1.1 cancontroller............................... ................................................... ............ 22 4.1.2 ram .......................................... ................................................... ................ 22 4.1.3 cpuinterface ................................ ................................................... ............ 22 4.1.4 i/oports .................................... ................................................... ................ 23 4.1.5 programmableclockoutput.................... ................................................... .. 23 4.2 addressmap.................................... ................................................... ...................... 23 4.3 canmessageobjects............................ ................................................... ............... 23 5. accharacteristics.............................. ................................................... ........................... 26 6. physicaldimensions............................. ................................................... ......................... 42 7. orderinginformation............................ ................................................... .......................... 45 ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 4 of 45 1-888-824-4184 ? listoffigures figure1.ia8252744pinplccpackagediagram ..... ................................................... ........... 8 figure2.ia8252744pinqfppackagediagram ...... ................................................... ............ 9 figure3.ia82527functionalblockdiagram........ ................................................... ................ 21 figure4.mosi/misoconnection .................... ................................................... ....................... 22 figure5.ia82527addressmap ..................... ................................................... ...................... 24 figure6.ia82527messageobjectstructure ........ ................................................... ............... 25 figure7.mode0andmode1generalbustiming .... ................................................... .......... 29 figure8.mode0andmode1readytimingforread cycle.............................................. ...... 30 figure9.mode0andmode1readytimingforwrite cyclewithnowritepending ................ 30 figure10.mode0&mode1readytimingforwrite cyclewithwriteactive........................... 3 1 figure11.mode2generalbustiming .............. ................................................... .................. 33 figure12.mode3,asynchronousoperation,readcy cle ................................................ ...... 35 figure13.mode3,asynchronousoperation,writec ycle ............................................... ....... 36 figure14.mode3,synchronousoperation,readcyc letiming .......................................... .. 38 figure15.mode3,synchronousoperation,writecy cletiming......................................... .... 39 figure16.serialinterfacemode,icp=0andcp= 0 ................................................. .............. 41 figure17.serialinterfacemode,icp=1andcp= 1 ................................................. .............. 41 figure18.44pinplccphysicaldimensions........ ................................................... .............. 43 figure19.44pinqfpphysicaldimensions ......... ................................................... ............... 44 listoftables table1.ia8252744pinplccpinlist............. ................................................... ..................... 8 table2.ia8252744pinqfppinlist .............. ................................................... ...................... 9 table3.ia82527pin/signaldescriptions.......... ................................................... ................... 10 table4.ia82527absolutemaximumratings ......... ................................................... ............. 18 table5.ia82527thermalcharacteristics.......... ................................................... .................. 18 table6.ia82527dcparameters.................... ................................................... ..................... 19 table7.ia82527isophysicallayerdcparameters. ................................................... ......... 20 table8.mode0andmode1generalbusandreadyt iming .............................................. .... 27 table9.mode2generalbustiming ................ ................................................... ................... 32 table10.mode3asynchronousoperationtiming .... ................................................... .......... 34 table11.mode3synchronousoperationtiming..... ................................................... ........... 37 table12.serialinterfacemodetiming ............ ................................................... .................... 40 table13.44pinplccphysicaldimensions ......... ................................................... .............. 43 table14.44pinqfpphysicaldimensions .......... ................................................... ............... 44 table15.ia82527orderinginformation............ ................................................... ................... 45 ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 5 of 45 1-888-824-4184 ? 1. introduction theinnovasicsemiconductoria82527controllerarea network(can)serialcommunications controllerisaform,fit,andfunctionreplacement fortheoriginalintel ? 82527serial communicationscontroller. thesedevicesareproducedusinginnovasicsmanage diclifetimeextensionsystem (miles?).thiscloningtechnology,whichproduces replacementicsbeyondsimple emulations,ensurescompletecompatibilitywiththe originaldevice,includingany undocumentedfeatures.additionally,miles?capt urestheclonedesigninsuchawaythat productionoftheclonecancontinueevenassilico ntechnologyadvances. theia82527serialcommunicationscontrollerreplac estheobsoleteintel ? 82527device, allowinguserstoretainexistingboarddesigns,so ftwarecompilers/assemblers,andemulation tools,therebyavoidingexpensiveredesignefforts. note thisdatasheetcontainspreliminaryinformationfo rthe innovasicsemiconductoria82527serialcommunicatio ns controller.thefinalizeddatasheetthatdocument sall necessaryengineeringinformationabouttheia82527 willbe availablewhenthedevicenearscompletioninq220 08. 1.1 generaldescription controllerareanetwork(can)protocolusesamulti mastercsma/cr(carriersense,multiple accesswithcollisionresolution)bustotransferm essageobjectsbetweennetworknodes. theia82527supportscanspecification2.0partaa ndb,standardandextendedmessage frames,andhasthecapabilitytotransmit,receive ,andperformmessagefilteringonextended messageframes. theia82527canstore15messageobjectsof8byte datalength.eachmessageobjectcanbe configuredaseithertransmitorreceiveexceptfor thelastmessageobject,whichisreceive only.thelastmessageobjectalsoprovidesaspec ialacceptancemaskdesignedtoallow selectgroupsofdifferentmessageidentifierstob ereceived. theia82527alsoprovidesaprogrammableacceptance maskthatallowsuserstoglobally maskanyidentifierbitsoftheincomingmessage. thisglobalmaskcanbeusedforboth standardandextendedmessageframes. ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 6 of 45 1-888-824-4184 ? 1.2 features theprimaryfeaturesoftheia82527areasfollows: ? canprotocolsupport o specification2.0,partaandpartb o standarddataandremoteframes o extendeddataandremoteframes ? canbusinterface o configurableinputcomparator o configurableoutputdriver ? globalmask,programmable o standardmessageidentifier o extendedmessageidentifier ? messageobjects o 14transmit/receivebuffers o 1receivebufferwithprogrammablemask ? programmablebitrate ? flexiblestatusinterface ? cpuinterfaceoptions o 16bitmultiplexedintel ? architecture o 8bitmultiplexedintel ? architecture o 8bitmultiplexednonintel ? architecture o 8bitnonmultiplexednonintel ? architecture o serial(spi) ? i/oports(2) o 8bit o bidirectional ? flexibleinterruptstructure ? programmableclockoutput amoredetaileddescriptionoftheia82527,includi ngthefeatureslistedabove,isprovidedin section4. ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 7 of 45 1-888-824-4184 ? 2. packagingandpindescriptions 2.1 packagesandpinouts theinnovasicsemiconductoria82527canserialcomm unicationscontrollerisavailablein thefollowingpackages: ? 44pinplasticleadedchipcarrier(plcc) ? 44pinquadflatpack(qfp) the44pinplccpackageisshowninfigure1/table 1,andthe44pinqfppackageisshown infigure2/table2. detaileddescriptionsofpin/signalfunctionsarep rovidedinsection2.2(table3). note table1(plccpackage)andtable2(qfppackage)pr ovide numericalindexesofpinnames.table3providesa n alphabeticalindexofpinandsignaldescriptions. ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 8 of 45 1-888-824-4184 ? figure1.ia8252744pinplccpackagediagram table1.ia8252744pinplccpinlist pin name pin name pin name pin name 1 v cc 12 p2.5 23 v ss1 34 ad12/d4/p1.4 2 a2/ad2/csas 13 p2.4 24 int_n/v cc /2 35 ad11/d3/p1.3 3 a1/ad1/cp 14 p2.3 25 tx1 36 ad10/d2/p1.2 4 a0/ad0/icp 15 p2.2 26 tx0 37 ad9/d1/p1.1 5 ale/as 16 p2.1 27 clkout 38 ad8/d0/p1.0 6 rd_n/e 17 p2.0 28 ready/miso 39 a7/ad7 7 wr_n/wrl_n/rw_n 18 xtal1 29 reset_n 40 a6/ad6/sc lk 8 cs_n 19 xtal2 30 mode1 41 a5/ad5 9 dsack0_n 20 v ss2 31 ad15/d7/p1.7 42 a4/ad4/mosi 10 wrh_n/p2.7 21 rx1 32 ad14/d6/p1.6 43 a3/ad3/ste 11 int_n/p2.6 22 rx0 33 ad13/d5/p1.5 44 mode0 ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 9 of 45 1-888-824-4184 ? figure2.ia8252744pinqfppackagediagram table2.ia8252744pinqfppinlist pin name pin name pin name pin name 1 wr_n/wrl_n/rw_n 12 xtal1 23 reset_n 34 a6/ad6/sc lk 2 cs_n 13 xtal2 24 mode1 35 a5/ad5 3 dsack0_n 14 v ss2 25 ad15/d7/p1.7 36 a4/ad4/mosi 4 wrh_n/p2.7 15 rx1 26 ad14/d6/p1.6 37 a3/ad3/ste 5 int_n/p2.6 16 rx0 27 ad13/d5/p1.5 38 mode0 6 p2.5 17 v ss1 28 ad12/d4/p1.4 39 v cc 7 p2.4 18 int_n/v cc /2 29 ad11/d3/p1.3 40 a2/ad2/csas 8 p2.3 19 tx1 30 ad10/d2/p1.2 41 a1/ad1/cp 9 p2.2 20 tx0 31 ad9/d1/p1.1 42 a0/ad0/icp 10 p2.1 21 clkout 32 ad8/d0/p1.0 43 ale/as 11 p2.0 22 ready/miso 33 a7/ad7 44 rd_n/e ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 10 of 45 1-888-824-4184 ? 2.2 pin/signaldescriptions descriptionsofthepinandsignalfunctionsforth eia82527serialcommunicationscontroller areprovidedintable3. severaloftheia82527pinshavedifferentfunction sdependingontheoperatingmodeofthe device.eachofthedifferent signals supportedbyapinislistedanddefinedintable 3,indexed alphabeticallyinthefirstcolumnofthetable.a dditionally,thenameofthepinassociatedwith thesignalaswellasthepinnumbersforboththe plccandqfppackagesareprovidedinthe pincolumn.ifthesignalandpinnamesarethe same,noentryisprovidedinthepinname column. table3.ia82527pin/signaldescriptions pin signal name plcc qfp description a0 a0 /ad0/icp 4 42 a1 a1 /ad1/cp 3 41 a2 a2 /ad2/csas 2 40 a3 a3 /ad3/ste 43 37 a4 a4 /ad4/mosi 42 36 a5 a5 /ad5 41 35 a6 a6 /ad6/sclk 40 34 a7 a7 /ad7 39 33 a ddressbits 7 C 0 .input.mode3. whentheia82527isconfiguredtooperateinthe8 bitnon multiplexednonintel ? architecturemode(mode3),theselines providethe8bitaddressbusinputtothedevice. ad0 a0/ ad0 /icp 4 42 ad1 a1/ ad1 /cp 3 41 ad2 a2/ ad2 /csas 2 40 ad3 a3/ ad3/ ste 43 37 ad4 a4/ ad4 /mosi 42 36 ad5 a5/ ad5 41 35 ad6 a6/ ad6 /sclk 40 34 ad7 a7/ ad7 39 33 ad8 ad8 /d0/p1.0 38 32 ad9 ad9 /d1/p1.1 37 31 ad10 ad10 /d2/p1.2 36 30 ad11 ad11 /d3/p1.3 35 29 ad12 ad12 /d4/p1.4 34 28 ad13 ad13 /d5/p1.5 33 27 ad14 ad14 /d6/p1.6 32 26 ad15 ad15 /d7/p1.7 31 25 a ddress/ d atabits 15 C 0 .input/output.mode1. whentheia82527isconfiguredtooperateinthe16 bitmultiplexed intel ? architecturemode(mode1),theselinesprovideth e16bit addressbus(input)andthe16bitdatabus(input/ output)forthe device. ale ale /as 5 43 a ddress l atch e nable.input.activehigh.mode0andmode1. whentheia82527isconfiguredtooperateineither the8bit multiplexedintel ? architecturemode(mode0)orthe16bit multiplexedintel ? architecturemode(mode1),thissignallatchesth e addressintothedeviceduringtheaddressphaseof thebuscycle. continued ... ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 11 of 45 1-888-824-4184 ? table3.ia82527pin/signaldescriptions , continued pin signal name plcc qfp description as ale/ as 5 43 a ddress s trobe.input.activehigh.mode2. whentheia82527isconfiguredtooperateineither the8bit multiplexednonintel ? architecturemode(mode2),thissignallatches theaddressintothedeviceduringtheaddressphas eofthebus cycle. note :iftheia82527isconfiguredtooperateinmode 3(8bitnon multiplexednonintel ? architecture),thispinmustbetiedhigh. clkout 27 21 cl oc k out .output(pushpull). thisoutputprovidesaprogrammableclockfrequency .the frequencyissetviatheclockoutregister(1fh)an dcanrangefrom thefrequencyofthe xtal (crystal)inputtoxtal/ n ,where n canbean integervaluefrom2through15.thisoutputallow stheia82527to clockotherdevicessuchasthehostcpu. cp a1/ad1/ cp 3 41 c lock p hase.input.serialinterfacemode. whenthisinputisalogic0,dataaresampledont herisingedgeof sclk .whenthisinputisalogic1,dataaresampledo nthefalling edgeof sclk . cs_n 8 2 c hip s elect.input.activelow(modes0C3);selectable activelevel (serialinterfacemode). whentheia82527isconfiguredtooperateinoneof theparallel interfacemodes(modes0C3)ortheserialinterface mode,thisinput, duringitsactivestate,selectsthedeviceallowin gcpuaccess. forserialinterfacemodeoperation,theactivesta teisselectable (i.e.,eitherhighorlow)viatheia8257 csas pin. csas a2/ad2/ csas 2 40 c hip s elect a ctive s tate.input.serialinterfacemode. whenthisinputisalogic0,the cs_n inputisconfiguredtofunction activelow.whenthisinputisalogic1,the cs_n inputisconfigured tofunctionactivehigh. d0 ad8/ d0 /p1.0 38 32 d1 ad9/ d1 /p1.1 37 31 d2 ad10/ d2 /p1.2 36 30 d3 ad11/ d3 /p1.3 35 29 d4 ad12/ d4 /p1.4 34 28 d5 ad13/ d5 /p1.5 33 27 d6 ad14/ d6 /p1.6 32 26 d7 ad15/ d7 /p1.7 31 25 d atabits 7 C 0 .input/output.mode3. whentheia82527isconfiguredtooperateinthe8 bitnon multiplexednonintel ? architecturemode(mode3),theselines providethe8bitdatabustothedevice. continued ... ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 12 of 45 1-888-824-4184 ? table3.ia82527pin/signaldescriptions , continued pin signal name plcc qfp description dsack0_n 9 3 d ataand s ize ack nowledge 0 .output.activelow(opendrainwith activepullup).mode3(asynchronousoperation). whentheia82527isconfiguredtooperateinthe8 bitnon multiplexednonintel ? architecturemode(mode3),thissignal functionsasfollows:whenthecpureadsfromthe ia82527, dsack0_n activelowindicatesthatthedataarevalid;when thecpu writestotheia82527, dsack0_n activelowindicatesthatthedata havebeenreceived. e rd_n/ e 6 44 e nable.input.activehigh.mode3(asynchronous) . whentheia82527isconfiguredtooperateinthe8 bitnon multiplexednonintel ? architecturemode(mode3),thissignal functionsasfollows:whenthecpureadsfromorw ritestothe ia82527, e activehighindicatesthattheaddressisvalid. icp a0/ad0/ icp 4 42 i dle c lock p olarity.input.serialinterfacemode. whenthisinputisalogic0,thepolarityforthe idlestateof sclk is low.whenthisinputisalogic1,thepolarityfo rtheidlestateof sclk ishigh. int_n /v cc /2 24 18 int_n int_n /p2.6 11 5 int errupt.output(opencollector).activelow. ontheia82527,twopinscanprovidetheinterrupt ( int_n )output; however,dependingonthesettingofthemuxbitin thecpu interfaceregister(02h),onlyoneofthepinswill serveasthesource of int_n asfollows: ? plccpackage: - whenthemuxbitofthecpuinterfaceregisteris0 ,pin 24functionsasthe int_n outputandpin11functionsas p2.6 . - whenthemuxbitofthecpuinterfaceregisteris1 ,pin 11functionsasthe int_n outputandpin24functionsas v cc /2 . ? qfppackage: - whenthemuxbitofthecpuinterfaceregisteris0 ,pin 18functionsasthe int_n outputandpin5functionsas p2.6 . - whenthemuxbitofthecpuinterfaceregisteris1 ,pin 5functionsasthe int_n outputandpin18functionsas v cc /2 . continued ... ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 13 of 45 1-888-824-4184 ? table3.ia82527pin/signaldescriptions , continued pin signal name plcc qfp description miso ready/ miso 28 22 m aster i n s lave o ut.output(opendrain).serialinterfacemode. whentheia82527isconfiguredtooperatewithase rialinterface, miso istheserialdataoutput. mode0 44 38 mode1 30 24 moden (n=1or0).input. thelogiclevelsatthemode0andmode1inputsdete rminethe operatingmode(i.e.,interfacetype)oftheia8252 7asfollows: mode1 mode0 interfacetype 0 0 8bitmultiplexedintel ? 0 1 16bitmultiplexedintel ? 1 0 8bitmultiplexednonintel ? 1 1 8bitnonmultiplexednonintel ? the mode1 and mode0 inputsarealsousedtoestablishtheserial interfacemodeasfollows:whentheia82527isres et,if ? mode1 =0 ? mode0 =0 ? rd_n =0 ? wr_n =0 theserialinterfacemodewillbeselected. the mode1 and mode0 pinsareinternallyconnectedtoweakpull downs.thesepinswillbepulledlowduringreset ifunconnected. followingreset,thesepinswillfloat. mosi a4/ad4/ mosi 42 36 m aster o ut s lave i n.input.serialinterfacemode. whentheia82527isconfiguredtooperatewithase rialinterface, mosi istheserialdatainput. continued ... ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 14 of 45 1-888-824-4184 ? table3.ia82527pin/signaldescriptions , continued pin signal name plcc qfp description p1.0 ad8/d0/ p1.0 38 32 p1.1 ad9/d1/ p1.1 37 31 p1.2 ad10/d2/ p1.2 36 30 p1.3 ad11/d3/ p1.3 35 29 p1.4 ad12/d4/ p1.4 34 28 p1.5 ad13/d5/ p1.5 33 27 p1.6 ad14/d6/ p1.6 32 26 p1.7 ad15/d7/ p1.7 31 25 p ort 1 ,bit n (n=7C0).input/output(generalpurpose).mode0 , mode2,andserialinterfacemode. port1bits p1.7 C p1.0 canbeindividuallyprogrammedasinputsor outputs.programmingisaccomplishedbywritingto thep1conf register(9fh).the8bitsofthep1confregister, p1conf7C p1conf0,corresponddirectlytopins p1.7 C p1.0 .writinga0toabit inthep1confregistercausesthecorrespondingpin tobe configuredasahighimpedanceinput.writinga1 toabitinthe p1confregistercausesthecorrespondingpintobe configuredas apushpulloutput.allport1pinshaveweakpull upsuntiltheportis configuredbywritingtothep1confregister.the defaultvalueof thep1confregisterfollowingaresetis00h. dataarereadfromport1viathep1inregister(bf h).alogic0for anybitinthisregistermeansthatalogic0wasr eadfromthe correspondingpin;alogic1foranybitmeansthat alogic1wasread fromthecorrespondingpin.thedefaultvalueoft hep1inregister followingaresetisffh. dataarewrittentoport1viathep1outregister( dfh).writinga logic0toanybitinthisregistermeansthatalo gic0iswrittentothe correspondingpin;writingalogic1toanybitmea nsthatalogic1is writtentothecorrespondingpin.thedefaultvalu eofthep1out registerfollowingaresetis00h. p2.0 17 11 p2.1 16 10 p2.2 15 9 p2.3 14 8 p2.4 13 7 p2.5 12 6 p2.6 int_n/ p2.6 11 5 p2.7 wrh_n/ p2.7 10 4 p ort 2 ,bit n (n=7C0).input/output. port2bits p2.7 C p2.0 ,canbeindividuallyprogrammedasinputsor outputs.programmingisaccomplishedbywritingto thep2conf register(afh).the8bitsofthep2confregister, p2conf7C p2conf0,corresponddirectlytopins p2.7 C p2.0 .writinga0toabit inthep2confregistercausesthecorrespondingpin tobe configuredasahighimpedanceinput.writinga1 toabitinthe p2confregistercausesthecorrespondingpintobe configuredas apushpulloutput.allport2pinshaveweakpull upsuntiltheportis configuredbywritingtothep2confregister.the defaultvalueof thep1confregisterfollowingaresetis00h. dataarereadfromport2viathep2inregister(cf h).alogic0for anybitinthisregistermeansthatalogic0wasr eadfromthe correspondingpin;alogic1foranybitmeansthat alogic1wasread fromthecorrespondingpin.thedefaultvalueoft hep2inregister followingaresetisffh. dataarewrittentoport2viathep2outregister( efh).writinga logic0toanybitinthisregistermeansthatalo gic0iswrittentothe correspondingpin;writingalogic1toanybitmea nsthatalogic1is writtentothecorrespondingpin.thedefaultvalu eofthep2out registerfollowingaresetis00h. ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 15 of 45 1-888-824-4184 ? continued ... table3.ia82527pin/signaldescriptions , continued pin signal name plcc qfp description rd_n rd_n /e 6 44 r ea d .input.activelow.mode0andmode1. when rd_n isasserted(low),itcausestheia82527todrive thedata fromthelocationbeingreadontothedatabus. ready ready /miso 28 22 ready .output(opendrain).activehigh.mode0andm ode1. whenreadyisasserted(high),itsignalsthecompl etionofabus cycle.thereadyoutputisprovidedtoforcesyste mcpuwaitstates asrequired. reset_n 29 23 reset .input.activelow. whenthe reset_n signalisasserted(low),theia82527isinitializ ed. therearetworesetsituations: coldreset .thisisapoweronreset:asv cc isdriventoavalid level(poweron),the reset_n signalmustbedrivenlowfora minimumof1msmeasuredfromavalidv cc level.nofallingedge onthereset_npinisrequiredduringacoldreset. warmreset .forthisreset,v cc remainsatavalidlevel(i.e.,power isalreadyonandremainson)while reset_n isdrivenlowfora minimumof1ms. rw_n wr _ n/wrl _ n/ rw _ n 7 1 r ead w rite.input.activehigh(read)activelow(write ).mode3. when rw_n ishigh,itsignalsareadcycle.when rw_n islow,it signalsawritecycle. rx0 22 16 rx1 21 15 receive( rx ),lines 0 and 1 .input. pins rx0 and rx1 aretheinputstotheia82527fromthecontroller areanetwork(can)buslines.thesepinsconnecti nternallytothe receiverinputcomparator.serialdatafromtheca nbuscanbe receivedusingboth rx0 and rx1 orbyusingonly rx0 asfollows: ? whenthecobybitinthebusconfigurationregister (2fh)is a0, rx0 and rx1 areconnectedtotheinputcomparator.( rx0 isconnectedtothenoninvertinginputandrx1is connected totheinvertinginput.)arecessivelevelisread when rx0 > rx1 .adominantlevelisreadwhen rx1 > rx0 . ? whenthecobybitinthebusconfigurationregister (2fh)is a1,inputcomparisonisdisabled,and rx0 ,whichisstill connectedtothenoninvertinginputofthecompara tor,isthe canbuslineinput.forthisconfiguration,thedc r0bitofthe busconfigurationregistermustbea0. afteracoldreset(poweron),thedefaultconfigur ationistheuseof both rx0 and rx1 forthecanbusinput. sclk a6/ad6/ sclk 40 34 s erial cl oc k .input.serialinterfacemode. the sclk pinistheserialclockinputtotheia82527(slav edevice). theclocksignalisprovidedbythemasterdevice. continued ... ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 16 of 45 1-888-824-4184 ? table3.ia82527pin/signaldescriptions , continued pin signal name plcc qfp description ste a3/ad3/ ste 43 37 s ynchronization t ransmission e nable.input.serialinterfacemode. thelogiclevelatthe ste pinenablesthetransmissionofthe synchronizationbytesthroughtheia82527 miso pinwhilethemaster devicetransmitstheaddressandcontrolbyteasfo llows: ? whenalogic0isplacedonthe ste pin,thesynchronization bytessentthroughthe miso pinare00hand00h. ? whenalogic1isplacedonthe ste pin,thesynchronization bytessentthroughthe miso pinareaahand55h. theia82527sendsthesynchronizationbytesaftert he cs_n signal hasbeenasserted(low). tx0 26 20 tx1 25 19 transmit( tx ),lines 0 and 1 .output(pushpull). pins tx0 and tx1 aretheoutputsfromtheia82527tothecontroller areanetwork(can)buslines. duringarecessivebit, tx0 ishighand tx1 islow.duringadominant bit, tx0 islowand tx1 ishigh. v cc 1 39 power( v cc ). thispinprovidespowerfortheia82527device.it mustbe connectedtoa+5vdcpowersource. v cc /2 int_n/ v cc /2 24 18 referencevoltage,isophysicallayer( v cc /2 ).output. the v cc /2 pinprovidesareferencevoltagefortheisolows peed physicallayer: ? 2. 38vdc(minimum)to2.60vdc(maximum) (v cc =+5.00v;i out 75a) thispinonlyfunctionsas v cc /2 whenthemuxbitofthecpu interfaceregister(02h)is1. v ss1 23 17 ground,digital( v ss1 ). thispinprovidesthedigitalground(0v)forthei a82527.itmustbe connectedtoav ss boardplane. v ss2 20 14 ground,analog( v ss2 ). thispinprovidestheground(0v)fortheia82527a nalogcomparator. itmustbeconnectedtoav ss boardplane. continued ... ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 17 of 45 1-888-824-4184 ? table3.ia82527pin/signaldescriptions , continued pin signal name plcc qfp description wr_n wr _ n /wrl _ n/rw _ n 7 1 wr ite.input.activelow.mode0. when wr_n isasserted(low),itsignalsawritecycle. wrh_n wrh_n /p2.7 10 4 wr ite h ighbyte.input.activelow.mode1. when wrh_n isasserted(low),itsignalsawritecycleforth ehigh byteofdata(bits15C8). wrl_n wr _ n/ wrl _ n /rw _ n 7 1 wr ite l owbyte.input.activelow.mode1. when wrl_n isasserted(low),itsignalsawritecycleforth elowbyte ofdata(bits7C0). xtal1 18 12 crystal( xtal ) 1 .input. the xtal1 pinistheinputconnectionforanexternalcrysta lthat drivestheia82527internaloscillator.(whenane xternalcrystalis used,itisconnectedbetweenthispinandthe xtal2 pinseenext tableentry.) note: ifanexternaloscillatororclocksourceisused todrivethe ia82527insteadofacrystal,the xtal1 pinistheinputforthisclock source. xtal2 19 13 crystal( xtal ) 2 .output(pushpull). the xtal2 pinistheoutputconnectionforanexternalcryst althat drivestheia82527internaloscillator.(whenane xternalcrystalis used,itisconnectedbetweenthispinandthe xtal1 pinsee previoustableentry.) note: ifanexternaloscillatororclocksourceisused todrivethe ia82527insteadofacrystal, xtal2 mustbeleftunconnected(i.e., mustbefloated).additionally,the xtal2 outputmustnotbeusedasa clocksourceforothersystemcomponents. ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 18 of 45 1-888-824-4184 ? 3. maximumratings,thermalcharacteristics,anddc parameters fortheinnovasicsemiconductoria82527serialcomm unicationscontroller,theabsolute maximumratings,thermalcharacteristics,anddcpa rametersareprovidedintables4C6, respectively. additionally,thedcparametersoftheisophysical layerareprovidedintable7. note thevaluesprovidedinthefollowingtablesarepre liminary. table4.ia82527absolutemaximumratings parameter rating storagetemperature ?65cto+150c casetemperatureunderbias ?65cto+120c supplyvoltagewithrespecttovss ?0.5vto+6.5v voltageonpinsotherthansupplywithrespecttov ss ?0.5vto+5.5v table5.ia82527thermalcharacteristics symbol characteristic value units t a ambienttemperature userdetermined c p int deviceinternalpowerdissipation i dd xv dd w p i/o i/opinpowerdissipation userdetermined w p d totalpowerdissipation p int +p i/o w 44pinplccpackage tobedetermined ja 44pinqfppackage tobedetermined c/w t j averagejunctiontemperature t a +(p d x ja ) c ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 19 of 45 1-888-824-4184 ? table6.ia82527dcparameters symbol parameter pin(s) minimum maximum units notes v cc supplyvoltage 4.5 5.5 v ad7Cad0 ?0.5 0.5 mode3 p1.7Cp1.0, p2.7Cp2.0 0.3(v cc ) notconnectedtoahost cpu rx0 0.5 comparatorbypassed v il voltage,inputlow ?0.5 0.8 v allotherpins p1.7Cp1.0, p2.7Cp2.0 0.7(v cc ) notconnectedtoahost cpu reset_n 3.0 v cc +0.5 reset_n hysteresis=200mv rx0 4.0 comparatorbypassed v ih voltage,inputhigh 3.0 v cc +0.5 v allotherpins tx0,tx1 seetable7 v ol voltage,outputlow 0.45 v allotherpins;i ol =1.6ma clkout 0.8(v cc ) i oh =?80a tx0,tx1 seetable7 v oh voltage,outputhigh v cc ?0.8 v allotherpins;i oh =?200a i leak inputleakagecurrent 10 a v ss ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 21 of 45 1-888-824-4184 ? 4. functionaldescription 4.1 hardwarearchitecture ablockdiagramoftheia82527canserialcommunica tionscontrollerisshowninfigure3. theprimaryarchitecturalfeaturesofthedevicear easfollows: ? controllerareanetwork(can)controller ? ram ? cpuinterface ? i/oports ? programmableclockoutput thesefeaturesarebrieflydescribedinthefollowi ngsubsections. figure3.ia82527functionalblockdiagram ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 22 of 45 1-888-824-4184 ? 4.1.1 cancontroller thecancontrollerblockoftheia82527supportsth einterfacetothecanbusviathe rx0,rx1 , tx0 ,and tx1 lines.thecancontrollermanagesthetransceiver logic,errormanagementlogic, andthemessageobjects,controllingthedatastrea mbetweentheram(paralleldata)andthe canbus(serialdata). 4.1.2 ram theramblockoftheia82527providestheinterface bufferbetweenthesystemcpuandthe canbus.theia82527ramprovidesstoragefor15m essageobjectsof8bytedatalength. theramisaninterleavedaccessmemory,whichmean sthataccesstotheramistimeshared betweenthecpuinterfacelogicandthecanbus. 4.1.3 cpuinterface theia82527iscapableofinterfacingtomanycommo nlyusedmicrocontrollers.therearefour parallelinterfaceoptionsandaserialinterfaceo ption. differentinterfaceoptions,ormodes,areselected usinginterfacemodepins, mode1 and mode0 .theparallelinterfacemodesthatcanbeselecte dareasfollows: ? 8bitintel ? multiplexedaddressanddatabuses ? 16bitintel ? multiplexedaddressanddatabuses ? 8bitnonintel ? multiplexedaddressanddatabuses ? 8bitnonmultiplexedaddressanddatabuses theserialinterfacemodeisfullycompatiblewith themotorola ? spiprotocolandwillinterfaceto mostcommonlyusedserialinterfaces.theseriali nterfaceisimplementedinslavemodeonly, andrespondstothemasterusingthespeciallydesi gnedserialinterfaceprotocol.theserial interfacemodeinterconnectionschemeisshowninf igure4. figure4.mosi/misoconnection ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 23 of 45 1-888-824-4184 ? 4.1.4 i/oports theia82527providestwo8bitlowspeedinput/outp ut(i/o)ports.dependingonthecpu interfacemodeselected,atleast7andupto16i/ olinesareavailable.eachi/olineis individuallyprogrammabletofunctioneitherasan inputoranoutput. 4.1.5 programmableclockoutput usinganoscillator,clockdividerregister,anda drivercircuit,theia82527providesa programmableclockoutput.theoutputfrequencyra ngeavailableisfromtheexternalcrystal frequencytothatfrequencydividedby15.theclo ckoutputallowstheia82527todriveother devicessuchasthehostcpu. 4.2 addressmap theia82527includes2568bitlocationsthatprovi dedeviceconfigurationregistersand messagestorage.theaddressmapisshowninfigur e5. 4.3 canmessageobjects eachcanmessageobjecthasauniqueidentifierand canbeconfiguredaseithertransmitor receive,exceptforthelastmessageobject.thel astmessageobjectisareceiveonlybuffer withaspecialmaskdesigntoallowselectgroupso fdifferentmessageidentifierstobereceived. eachmessageobjectcontainscontrolandstatusbit s. allmessageobjectshaveseparatetransmitandrece iveinterruptsandstatusbitsthatallowthe hostcputodeterminewhenamessageframehasbeen sentorreceived.theia82527 implementsaglobalmaskingfeaturethatallowsthe usertogloballymaskanyidentifierbitsof theincomingmessage.thismaskisprogrammable,w hichpermitsapplicationspecific messageidentification. themessageobjectstructureisshowninfigure6. ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 24 of 45 1-888-824-4184 ? address register/message 00h controlregister 01h statusregister 02h cpuinterfaceregister 03h reserved 04C05h highspeedreadregister 06C07h globalmaskCstandard 08C0bh globalmaskCextended 0v0fh message15mask 10C1eh message1 1fh clkoutregister 20C2eh message2 2fh busconfigurationregister 30C3eh message3 3fh bittimingregister0 40C4eh message4 4fh bittimingregister1 50C5eh message5 5fh interruptregister 60C6eh message6 6fh reserved 70hC7eh message7 7fh reserved 80C8eh message8 8fh reserved 90C9eh message9 9fh p1confregister a0Caeh message10 afh p2confregister b0Cbeh message11 bfh p1inregister c0Cceh message12 cfh p2inregister d0Cdeh message13 dfh p1outregister e0Ceeh message14 efh p2outregister f0Cfeh message15 ffh serialresetaddressregister figure5.ia82527addressmap ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 25 of 45 1-888-824-4184 ? offset (baseaddress+n) messagecomponent +0 controlregister0 +1 controlregister1 +2 arbitrationregister0 +3 arbitrationregister1 +4 arbitrationregister2 +5 arbitrationregister3 +6 messageconfigurationregister +7 databyte0 +8 databyte1 +9 databyte2 +10 databyte3 +11 databyte4 +12 databyte5 +13 databyte6 +14 databyte7 figure6.ia82527messageobjectstructure ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 26 of 45 1-888-824-4184 ? 5. accharacteristics theaccharacteristicsoftheia82527areprovided inthefiguresandtablesofthischapter. theia82527canbeconfiguredtooperateinthefol lowingparallelandserialcpuinterface modes: ? mode0: 8bitmultiplexedintel ? architecture ? mode1: 16bitmultiplexedintel ? architecture ? mode2:8bitmultiplexednonintel ? architecture ? mode3: 8bitnonmultiplexednonintel ? architecture ? serialinterfacemode theaccharacteristicsofthesemodesinoperation ofareprovidedasfollows: ? mode0andmode1generalbustiming(table8/figur e7) ? mode0andmode1 ready timingforreadcycle(table8/figure8) ? mode0andmode1 ready timingforwritecyclewithnowritepending (table8/figure9) ? mode0&mode1 ready timingforwritecyclewithwritepending(table8 /figure10) ? mode2generalbustiming(table9/figure11) ? mode3,asynchronousoperation,readcycle(table1 0/figure12) ? mode3,asynchronousoperation,writecycle(table 10/figure13) ? mode3,synchronousoperation,readcycle(table11 /figure14) ? mode3,synchronousoperation,writecycle(table1 1/figure15) ? serialinterfacemode, icp =0and cp =0(table12/figure16) ? serialinterfacemode, icp =1and cp =1(table12/figure17) note thevaluesprovidedinthefollowingtablesandfig uresarepreliminary. ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 27 of 45 1-888-824-4184 ? table8.mode0andmode1generalbusand ready timing symbol parameter minimum maximum 1/t xtal oscillatorfrequency 8mhz 16mhz 1/t sclk systemclockfrequency 4mhz 10mhz 1/t mclk memoryclockfrequency 2mhz 8mhz t avll addressvalidto ale low 7.5ns t llax addressholdafter ale low 10ns t lhll ale hightime 30ns t llrl ale lowto rd_n low 20ns t clll cs_n lowto ale low 10ns t qvwh datasetupto wr_n or wrh_n high 27ns t whqx inputdataholdafter wr_n or wrh_n high 10ns t wlwh wr_n or wrh_n pulsewidth 30ns t whlh wr_n or wrh_n hightonextalehigh 8ns t whch wr_n or wrh_n highto cs_n high 0ns t rlrh rd_n pulsewidth thistimeislongenoughtoinitiateadoubleread cyclebyloadingthehighspeedregisters(04h, 05h),butistooshorttoreadfrom04hand05h (seet rldv ). 40ns t rldv rd_n lowtodatavalid (onlyforregisters02h,04h,05h) 0ns 55ns t rldv1 rd_n lowdatatodatavalid(forallregisters except02h,04h,05h) forreadcyclewithoutapreviouswrite 1.5t mclk +100ns t rldv1 rd_n lowdatatodatavalid(forallregisters except02h,04h,05h) forreadcyclewithapreviouswrite 3.5t mclk +100ns t rhdz datafloatafter rd_n high 0ns 45ns cs_n lowto ready setup (loadcapacitanceontheready output=50pf,v ol =1.0v) 32ns t clyv cs_n lowto ready setup (loadcapacitanceontheready output=50pf,v ol =0.45v) 40ns t wlyz wr_n or wrh_n lowto ready floatforawrite cycleifnopreviouswriteispending 145ns continued ... ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 28 of 45 1-888-824-4184 ? table8.mode0&mode1generalbusand ready timing , continued symbol parameter minimum maximum t whyz endoflastwriteto ready floatforawritecycleif apreviouswritecycleisactive 2t mclk +100ns t rlyz rd_n lowto ready float(forallregistersexcept 02h,04h,05h) forreadcyclewithoutapreviouswrite 2t mclk +100ns t rlyz rd_n lowto ready float(forallregistersexcept 02h,04h,05h) forreadcyclewithapreviouswrite 4t mclk +100ns t whdv wr_n hightooutputdatavalidonport1orport2 t mclk 2t mclk +500ns t copo clkout period ( cd v isthevalueloadedintheclkoutregister representingthe clkout divisor.) (cd v +1) ? t osc t chcl clkout highperiod ( cd v isthevalueloadedintheclkoutregister representingthe clkout divisor.) (cd v +1) ? ? t osc C 10 (cd v +1) ? ? t osc C15 ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 29 of 45 1-888-824-4184 ? figure7.mode0andmode1generalbustiming ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 30 of 45 1-888-824-4184 ? figure8.mode0andmode1 ready timingforreadcycle figure9.mode0andmode1 ready timingforwritecyclewithnowritepending ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 31 of 45 1-888-824-4184 ? figure10.mode0&mode1 ready timingforwritecyclewithwriteactive ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 32 of 45 1-888-824-4184 ? table9.mode2generalbustiming symbol parameter minimum maximum 1/t xtal oscillatorfrequency 8mhz 16mhz 1/t sclk systemclockfrequency 4mhz 10mhz 1/t mclk memoryclockfrequency 2mhz 8mhz t avsl addressvalidto as low 7.5ns t slax addressholdafter as low 10ns t eldz datafloatafter e low 0ns 45ns e hightodatavalidforregisters02h, 04h,05h 0ns 45ns e hightodatavalid(allregistersexcept for02h,04h,05h)forreadcyclewithouta previouswrite 1.5t mclk +100ns t ehdv e hightodatavalid(allregistersexcept for02h,04h,05h)forreadcyclewitha previouswrite 3.5t mclk +100ns t qvel datasetupto e low 30ns t elqx inputdataholdafter e low 20ns t eldv e lowtooutputdatavalidonport1/2 t mclk 2t mclk +500ns t ehel e hightime 45ns t shsl as hightime 30ns t rseh setuptimeof rw_n to e high 30ns t sleh as lowto e high 20ns t clsl cs_n lowto as low 20ns t elch e lowto cs_n high 0ns t copd clkout period (cd v isthevalueloadedintheclkout registerrepresentingthe clkout divisor.) (cd v +1) ? t osc t chcl clkout highperiod (cd v isthevalueloadedintheclkout registerrepresentingthe clkout divisor.) (cd v +1) ? ?t osc C10 (cd v +1) ? ?t osc C15 ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 33 of 45 1-888-824-4184 ? figure11.mode2generalbustiming ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 34 of 45 1-888-824-4184 ? table10.mode3asynchronousoperationtiming symbol parameter minimum maximum 1/t xtal oscillatorfrequency 8mhz 16mhz 1/t sclk systemclockfrequency 4mhz 10mhz 1/t mclk memoryclockfrequency 2mhz 8mhz t avcl addressor rw_n validto cs_n low setup 3ns cs_n lowtodatavalid (forhighspeedregisters02h,04h,and 05h) 0ns 55ns cs_n lowtodatavalid (forlowspeedregisters) readcyclewithoutpreviouswrite 0ns 1.5t mclk +100ns t cldv cs_n lowtodatavalid (forlowspeedregisters) readcyclewithpreviouswrite 0ns 3.5t mclk +100ns dsack0_n lowtooutputdatavalid (forhighspeedreadregisters) 23ns t kldv dsack0_n lowtooutputdatavalid (forlowspeedreadregisters) <0ns t chdv inputdataholdafter cs_n high 15ns t chdh outputdataholdafter cs_n high 0ns t chdz cs_n hightooutputdatafloat 35ns t chkh 1 cs_n highto dsack0_n =2.4v (anonchippullupwilldrive dsack0_n to approximately2.4v;anexternalpullupis requiredtodrivethissignaltoahigher voltage.) 0ns 55ns t chkh 2 cs_n highto dsack0_n =2.8v 150ns t chkz cs_n highto dsack0_n float 0ns 100ns t chcl cs_n widthbetweensuccessivecycles 25ns t chai cs_n hightoaddressinvalid 7ns t clch cs_n widthlow 65ns t dvch cpuwritedatavalidto cs_n high 20ns continued ... ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 35 of 45 1-888-824-4184 ? table10.mode3asynchronousoperationtiming , continued symbol parameter minimum maximum t clkl cs_n lowto dsack0_n low (forhighandlowspeedregisters) writecyclewithoutpreviouswrite 0ns 67ns t chkl endofpreviouswrite( cs_n high)to dsack0_n lowforawritecyclewitha previouswrite 0ns 2t mclk +145ns t copd clkout period (cd v isthevalueloadedintheclkout registerrepresentingthe clkout divisor.) (cd v +1)*t osc t chcl clkout highperiod (cd v isthevalueloadedintheclkout registerrepresentingthe clkout divisor.) (cd v +1)*?t osc C10 (cd v +1)*?t osc C15 figure12.mode3,asynchronousoperation,readcy cle ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 36 of 45 1-888-824-4184 ? figure13.mode3,asynchronousoperation,writec ycle ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 37 of 45 1-888-824-4184 ? table11.mode3synchronousoperationtiming symbol parameter minimum maximum 1/t xtal oscillatorfrequency 8mhz 16mhz 1/t sclk systemclockfrequency 4mhz 10mhz 1/t mclk memoryclockfrequency 2mhz 8mhz e hightodatavalid (forhighspeedregisters02h,04h, and5h) 55ns e hightodatavalid (forlowspeedregisters) readcyclewithoutpreviouswrite 1.5t mclk +100ns t ehdv e hightodatavalid (forlowspeedregisters) readcyclewithpreviouswrite 3.5t mclk +100ns t eldh dataholdafter e lowforareadcycle 5ns t eldz datafloatafter e low 35ns t eldv dataholdafter e lowforawritecycle 15ns t aveh addressand rw_n toesetup 25ns t elav addressand rw_n validafterefalls 15ns t cveh cs_n validto e high 0ns t elcv cs_n validafter e low 0ns t dvel datasetuptoelow 55ns t ehel e activewidth 100ns t avav startofawritecycleafteraprevious writeaccess 2t mclk t avcl addressor rw_n to cs_n lowsetup 3ns t chai cs_n highaddressinvalid 7ns t copd clkout period (cd v isthevalueloadedinthe clkoutregisterrepresentingthe clkout divisor.) (cd v +1)*t osc t chcl clkout highperiod (cd v isthevalueloadedinthe clkoutregisterrepresentingthe clkout divisor.) (cd v +1)*?t osc C10 (cd v +1)*?t osc +15 ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 38 of 45 1-888-824-4184 ? figure14.mode3,synchronousoperation,readcyc letiming ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 39 of 45 1-888-824-4184 ? figure15.mode3,synchronousoperation,writecy cletiming ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 40 of 45 1-888-824-4184 ? table12.serialinterfacemodetiming symbol parameter minimum maximum sclk serialportinterfaceclock 0.5mhz 8mhz t cyc 1/ sclk 125ns 2000ns t skhi minimumclockhightime 84ns t sklo minimumclocklowtime 84ns t lead enableleadtime 70ns t lag enablelagtime 109ns t acc accesstime 50ns t pdo maximumdataoutdelaytime 59ns t ho minimumdataoutholdtime 0ns t dis maximumdataoutdisabletime 665ns t setup minimumdatasetuptime 35ns t hold minimumdataholdtime 84ns t rise maximumtimeforinputtogofrom v ol tov oh 100ns t fall maximumtimeforinputtogofrom v oh tov ol 100ns t cs minimumtimebetweenconsecutive cs_n assertions 670ns t copd clkout period (cd v isthevalueloadedinthe clkoutregisterrepresentingthe clkout divisor.) (cd v +1)*t osc t chcl clkout highperiod (cd v isthevalueloadedinthe clkoutregisterrepresentingthe clkout divisor.) (cd v +1)*?t osc C10 (cd v +1)*?t osc +15 ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 41 of 45 1-888-824-4184 ? figure16.serialinterfacemode, icp =0and cp =0 figure17.serialinterfacemode, icp =1and cp =1 ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 42 of 45 1-888-824-4184 ? 6. physicaldimensions fortheinnovasicsemiconductoria82527serialcomm unicationsinterface,thephysical dimensionsfortheavailablepackagesareprovided inthefollowingfigures: ? 44pinplccpackage:figure18 ? 44pinqfppackage:figure19 atablespecifyingdimensionsaccompanieseachfigu re(tables13and14). ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 43 of 45 1-888-824-4184 ? figure18.44pinplccphysicaldimensions table13.44pinplccphysicaldimensions dimension minimum nominal maximum units numberofpins n 44 numberofpinsperside n1 11 pitch p 0.0500 overallheight a 0.1650 0.1800 moldedpackagethickness a2 0.1450 0.1600 standoff a1 0.0200 overallwidth e 0.6850 0.6950 overalllength d 0.6850 0.6950 moldedpackagewidth e1 0.6500 0.6560 moldedpackagelength d1 0.6500 0.6560 leadthickness c 0.0077 0.1160 leadwidth b 0.0130 0.0170 0.0210 pin1cornerchamfer ch 0.0420 0.0560 inches molddraftangletop 7.00 molddraftanglebottom 7.00 degrees ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 44 of 45 1-888-824-4184 ? figure19.44pinqfpphysicaldimensions table14.44pinqfpphysicaldimensions dimensions minimum nominal maximum units numberofpins n 44 numberofpinsperside n1 11 pitch p 0.031 overallheight a 0.096 moldedpackagethickness a2 0.079 standoff a1 0.010 footlength l 0.029 0.035 0.041 footprint(reference) (f) 0.063 overallwidth e 0.510 0.520 0.530 overalllength d 0.510 0.520 0.530 moldedpackagewidth e1 0.390 0.394 0.398 moldedpackagelength d1 0.390 0.394 0.398 leadthickness c 0.005 0.007 0.009 leadwidth b 0.012 0.015 0.018 pin1cornerchamfer ch 0.030 inches molddraftangletop 5.00 16.00 molddraftanglebottom 5.00 16.00 footangle 0.00 10.00 degrees ia82527 04may2007 canserialcommunicationscontroller asofproduction ver.00 preliminary copyright ? ?? ? 2007 en21070504-00 www.innovasic.com customer support: page 45 of 45 1-888-824-4184 ? 7. orderinginformation orderinginformationfortheinnovasicia82527seri alcommunicationscontrollerisprovidedin table15. table15.ia82527orderinginformation innovasic partnumber intel ? partnumber package status package type temperature grades ia82527plc44a as/an82527f8 standard 44pinplasticleaded chipcarrier(plcc) automotive ia82527ptq44a as/an82527f8 standard 44pinquadflat package(qfp) automotive ia82527plc44ar as/an82527f8 rohs 44pinplasticleaded chipcarrier(plcc) automotive ia82527ptq44ar as/an82527f8 rohs 44pinquadflat package(qfp) automotive otherpackagesandtemperaturegradesmaybeavaila bleforanadditionalcost,longerlead time,orboth. innovasicsemiconductor,inc. office: 505.883.5263 3737princetondrivene,suite130 fax: 505.883.547 7 albuquerque,nm871074327 tollfree: 1888.824.418 4 www.innovasic.com |
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